Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Shade: a fast instruction-set simulator for execution profiling
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Efficient software performance estimation methods for hardware/software codesign
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
Embedded program timing analysis based on path clustering and architecture classification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
Compilation-based software performance estimation for system level design
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Source-level execution time estimation of C programs
Proceedings of the ninth international symposium on Hardware/software codesign
Performance analysis with confidence intervals for embedded software processes
Proceedings of the 14th international symposium on Systems synthesis
Timed compiled-code simulation of embedded software for performance analysis of SOC design
Proceedings of the 39th annual Design Automation Conference
FPGA resource and timing estimation from Matlab execution traces
Proceedings of the tenth international symposium on Hardware/software codesign
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Journal of Systems and Software - Special issue: Rapid system prototyping
Fine-grained application source code profiling for ASIP design
Proceedings of the 42nd annual Design Automation Conference
Journal of VLSI Signal Processing Systems
Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Shared resource access attributes for high-level contention models
Proceedings of the 44th annual Design Automation Conference
Event-based re-training of statistical contention models for heterogeneous multiprocessors
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Fast cycle-approximate instruction set simulation
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Applying neural networks to performance estimation of embedded software
Journal of Systems Architecture: the EUROMICRO Journal
SciSim: a software performance estimation framework using source code instrumentation
WOSP '08 Proceedings of the 7th international workshop on Software and performance
Cycle-approximate retargetable performance estimation at the transaction level
Proceedings of the conference on Design, automation and test in Europe
Source-level timing annotation and simulation for a heterogeneous multiprocessor
Proceedings of the conference on Design, automation and test in Europe
Signature-Based Calibration of Analytical System-Level Performance Models
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
An efficient approach for system-level timing simulation of compiler-optimized embedded software
Proceedings of the 46th Annual Design Automation Conference
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Software performance simulation strategies for high-level embedded system design
Performance Evaluation
Performance modeling of embedded applications with zero architectural knowledge
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
TLM automation for multi-core design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
SOFSEM'11 Proceedings of the 37th international conference on Current trends in theory and practice of computer science
QUAD: a memory access pattern analyser
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Transactions on High-Performance Embedded Architectures and Compilers IV
Statistical Performance Modeling in Functional Instruction Set Simulators
ACM Transactions on Embedded Computing Systems (TECS)
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High-level cost and performance estimation, coupled with a fast hardware/software co-simulation framework, is a key enabler to a fast embedded system design cycle. Unfortunately, the problem of deriving such estimates without a detailed implementation available is difficult.In this paper we describe two approaches to solve software cost and performance estimation problem, and how they are used in an embedded system design environment. A source-based approach uses compilation onto a virtual instruction set, and allows one to quickly obtain estimates without the need for a compiler for the target processor. An object-based approach translates the assembler generated by the target compiler to “assembler-level,” functionally equivalent t C. In both cases the code is annotated with timing and other execution related information (e.g., estimated memory accesses) and is used as a precise, yet fast, software simulation model. We contrast the precision and speed of these two techniques comparing them with those obtainable by a state-of-the-art cycle-based processor model.