LISA—machine description language for cycle-accurate models of programmable DSP architectures
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Software performance estimation strategies in a system-level design tool
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Operating system based software generation for systems-on-chip
Proceedings of the 37th Annual Design Automation Conference
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Introduction to Hardware Abstraction Layers for SoC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A unified HW/SW interface model to remove discontinuities between HW and SW design
Proceedings of the 5th ACM international conference on Embedded software
Parallel programming of multi-processor SoC: a HW-SW interface perspective
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Evaluating the model accuracy in automated design space exploration
Microprocessors & Microsystems
Efficient implementation of native software simulation for MPSoC
Proceedings of the conference on Design, automation and test in Europe
Fast and accurate processor models for efficient MPSoC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Platform modeling for exploration and synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
System-level development of embedded software
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An Extended SystemC Framework for Efficient HW/SW Co-Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Current and future SoC will contain an increasing number of heterogeneous multiprocessor subsystems combined with a complex communication architecture to meet flexibility, performance and cost constraints. The early validation of such complex MP-SoC architectures is a key enabler to manage this complexity and thus to enhance design productivity.In this paper, we describe an abstract, high level CPU subsystem model that captures the specificities of such MP-SoC architectures, along with a timed co-simulation environment to perform early exploration of the entire HW/SW design. The model is based on the Hardware Abstraction Layer (HAL) concept allowing the validation of complex applications written on top of real-life operating systems. Experimentation with a MPEG4 application proves the interest of the proposed methodology.