The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
A retargetable, ultra-fast instruction set simulator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Methodology for hardware/software co-verification in C/C++ (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
System Design with SystemC
An ultra-fast instruction set simulator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
Proceedings of the conference on Design, automation and test in Europe
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Generic RTOS Model for Real-time Systems Simulation with SystemC
Proceedings of the conference on Design, automation and test in Europe - Volume 3
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Automatic Synthesis of High-Speed Processor Simulators
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Timed HW-SW cosimulation using native execution of OS and application SW
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
Cycle-approximate retargetable performance estimation at the transaction level
Proceedings of the conference on Design, automation and test in Europe
Introducing preemptive scheduling in abstract RTOS models using result oriented modeling
Proceedings of the conference on Design, automation and test in Europe
An effective synchronization approach for fast and accurate multi-core instruction-set simulation
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
A flexible hybrid simulation platform targeting multiple configurable processors SoC
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Source-level timing annotation for fast and accurate TLM computation model generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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In this article, we propose an extended SystemC framework that directly enables software simulation in SystemC. Although SystemC has been widely adopted for system-level simulation of hardware designs nowadays, to complete HW/SW co-simulation, it still requires an additional instruction set simulator (ISS) for software execution. However, the heavy intercommunication overheads between the two heterogeneous simulators would significantly slow down simulation performance. To deal with this issue, our proposed approach automatically generates high-speed and equivalent SystemC models for target software applications that can be directly integrated with hardware models for complete HW/SW co-simulation. In addition, to properly handle multitasking, an efficient OS model is devised to support accurate preemptive scheduling. Since both the generated application model and the OS model are constructed in SystemC modules, our approach avoids heavy intercommunication overheads and achieves over 1,000 times faster simulation than that of the conventional ISS-SystemC approach. Experimental results demonstrate that our extended SystemC approach can perform at 50 to 220 MIPS while offering accurate simulation results.