Validation in a component-based design flow for multicore SoCs
Proceedings of the 15th international symposium on System Synthesis
Multi-level software validation for NOC
Networks on chip
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
System-Level Performance Analysis in SystemC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Architecture-Level Performance Estimation for IP-Based Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
RTOS-centric hardware/software cosimulator for embedded system design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Introducing preemptive scheduling in abstract RTOS models using result oriented modeling
Proceedings of the conference on Design, automation and test in Europe
A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Integration, the VLSI Journal
Using a dataflow abstracted virtual prototype for HdS-design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Automatic instrumentation of embedded software for high level hardware/software co-simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TLM+ modeling of embedded HW/SW systems
Proceedings of the Conference on Design, Automation and Test in Europe
Assertion-based verification of RTOS properties
Proceedings of the Conference on Design, Automation and Test in Europe
A real-time application design methodology for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Increased accuracy through noise injection in abstract RTOS simulation
Proceedings of the Conference on Design, Automation and Test in Europe
System-level development of embedded software
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An Extended SystemC Framework for Efficient HW/SW Co-Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timed systemC waiting-state automata
VECoS'09 Proceedings of the Third international conference on Verification and Evaluation of Computer and Communication Systems
On the design space exploration through the Hellfire Framework
Journal of Systems Architecture: the EUROMICRO Journal
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To enable fast and accurate evaluation of HW/SW implementationchoices of on-chip communication, we presenta method to automatically generate timed OS simulationmodels. The method generates the OS simulation modelswith the simulation environment as a virtual processor.Since the generated OS simulation models use finalOS code, the presented method can mitigate the OS codeequivalence problem. The generated model also simulatesdifferent types of processor exceptions. This approach providestwo orders of magnitude higher simulation speedupcompared to the simulation using instruction set simulatorsfor SW simulation.