Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation

  • Authors:

  • Sang-Il Han;Soo-Ik Chae;Lisane Brisolara;Luigi Carro;Katalin Popovici;Xavier Guerin;Ahmed A. Jerraya;Kai Huang;Lei Li;Xiaolang Yan

  • Affiliations:

  • Seoul National University, South Korea;Seoul National University, South Korea;Informatics Institute, Federal University of Rio Grande do Sul, Brazil;Informatics Institute, Federal University of Rio Grande do Sul, Brazil;TIMA Laboratory, France;TIMA Laboratory, France;TIMA Laboratory, France;Institute of Vlsi Design, Zhejiang University, China;Institute of Vlsi Design, Zhejiang University, China;Institute of Vlsi Design, Zhejiang University, China

  • Venue:
  • Integration, the VLSI Journal
  • Year:
  • 2009

Quantified Score

Hi-index 0.00

Visualization

Abstract

As a solution for dealing with the design complexity of multiprocessor SoC architectures, we present a joint Simulink-SystemC design flow that enables mixed hardware/software refinement and simulation in the early design process. First, we introduce the Simulink combined algorithm/architecture model (CAAM) unifying the algorithm and the abstract target architecture. From the Simulink CAAM, a hardware architecture generator produces architecture models at three different abstract levels, enabling a trade-off between simulation time and accuracy. A multithread code generator produces memory-efficient multithreaded programs to be executed on the architecture models. To show the applicability of the proposed design flow, we present experimental results on two real video applications.