Fractional rate dataflow model and efficient code synthesis for multimedia applications
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Fractional Rate Dataflow Model for Efficient Code Synthesis
Journal of VLSI Signal Processing Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The CBP Parameter: A Module Characterization Approach for DSP Software Optimization
Journal of VLSI Signal Processing Systems
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Software synthesis from the dataflow interchange format
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Buffer memory optimization for video codec application modeled in Simulink
Proceedings of the 43rd annual Design Automation Conference
Memory-optimized software synthesis from dataflow program graphs with large size data samples
EURASIP Journal on Applied Signal Processing
A step towards unifying schedule and storage optimization
ACM Transactions on Programming Languages and Systems (TOPLAS)
Buffer optimization and dispatching scheme for embedded systems with behavioral transparency
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Memory-constrained block processing for DSP software optimization
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Integration, the VLSI Journal
Buffer sharing in CSP-like programs
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Look into details: the benefits of fine-grain streaming buffer analysis
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Buffer sharing in rendezvous programs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Heterogeneous design in functional DIF
Transactions on High-Performance Embedded Architectures and Compilers IV
Postscheduling buffer management trade-offs in streaming software synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Buffer Optimization and Dispatching Scheme for Embedded Systems with Behavioral Transparency
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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There has been a proliferation of block-diagram environments for specifying and prototyping digital signal processing (DSP) systems. These include tools from academia such as Ptolemy and commercial tools such as DSPCanvas from Angeles Design Systems, signal processing work system (SPW) from Cadence, and COSSAP from Synopsys. The block diagram languages used in these environments are usually based on dataflow semantics because various subsets of dataflow have proven to be good matches for expressing and modeling signal processing systems. In particular, synchronous dataflow (SDF) has been found to be a particularly good match for expressing multirate signal processing systems. One of the key problems that arises during synthesis from an SDF specification is scheduling. Past work on scheduling from SDF has focused on optimization of program memory and buffer memory under a model that did not exploit sharing opportunities. In this paper, we build on our previously developed analysis and optimization framework for looped schedules to formally tackle the problem of generating optimally compact schedules for SDF graphs. We develop techniques for computing these optimally compact schedules in a manner that also attempts to minimize buffering memory under the assumption that buffers will be shared. This results in schedules whose data memory usage is drastically lower than methods in the past have achieved. The method we use is that of lifetime analysis; we develop a model for buffer lifetimes in SDF graphs and develop scheduling algorithms that attempt to generate schedules that minimize the maximum number of live tokens under the particular buffer lifetime model. We develop several efficient algorithms for extracting the relevant lifetimes from the SDF schedule. We then use the well-known first-fit heuristic for packing arrays efficiently into memory. We report extensive experimental results on applying these techniques to several practical SDF systems and show improvements that average 50% over previous techniques, with some systems exhibiting up to an 83% improvement over previous techniques