Introduction to algorithms
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COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
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Scheduling of conditional process graphs for the synthesis of embedded systems
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Computers and Intractability: A Guide to the Theory of NP-Completeness
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IEEE Design & Test
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Multitasking on FPGA Coprocessors
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
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Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
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Memory-optimized software synthesis from dataflow program graphs with large size data samples
EURASIP Journal on Applied Signal Processing
Reliable multiprocessor system-on-chip synthesis
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Proceedings of the conference on Design, automation and test in Europe
An anomaly prevention approach for real-time task scheduling
Journal of Systems and Software
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing neural networks using hybrid particle swarm optimization
ISNN'05 Proceedings of the Second international conference on Advances in Neural Networks - Volume Part I
Allocation, scheduling and voltage scaling on energy aware MPSoCs
CPAIOR'06 Proceedings of the Third international conference on Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems
Shared buffer implementations of signal processing systems using lifetime analysis techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Flexible VLIW processor based on FPGA for efficient embedded real-time image processing
Journal of Real-Time Image Processing
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This work is motivated by the rapid increase in design complexity of many multi-function System on Chips. It proposes solutions to both resolve the hardware contention issues of non-preemptive processing elements shared among tasks, and to optimize cost. A software solution based on start time management is proposed to interleave task execution on processing elements. Algorithms are proposed to determine the required processing elements of selected types, when there is no knowledge on the release time of any task. For tasks whose release orders are known a priori, an optimal algorithm is presented if processing elements have the same cost, otherwise, if processing elements do not have the same cost, a pseudo polynomial-time algorithm based on dynamic programming is presented. The performance of the algorithms is also evaluated for general cases.