Reliable multiprocessor system-on-chip synthesis

  • Authors:

  • Changyun Zhu;Zhenyu (Peter) Gu;Robert P. Dick;Li Shang

  • Affiliations:

  • Queen's University, Kingston, ON, Canada;Northwestern University, Evanston, IL;Northwestern University, Evanston, IL;Queen's University, Kingston, ON, Canada

  • Venue:
  • CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
  • Year:
  • 2007

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Abstract

This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of communicating tasks, the proposed algorithm determines a processor core allocation, level of system-level and processor-level structural redundancy, assignment of tasks to processors, floorplan, and schedule in order to minimize system failure rate and area while meeting functionality and timing constraints. Changes to the thermal profile resulting from changes in allocation, assignment, scheduling, and floorplan are modeled and optimized during synthesis, as is the impact of thermal profile on temperature-dependent failure mechanisms. The proposed techniques have the potential to substantially increase MPSoC system mean time to failure compared to area-optimized solutions. If power densities are high and the dominant lifetime failure mechanisms are strongly dependent on temperature, our results indicate that thermal and structural redundancy optimization during synthesis have the potential to greatly increase MPSoC lifetime with low area cost.