Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A fast pseudo-boolean constraint solver
Proceedings of the 40th annual Design Automation Conference
The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
Proceedings of the 1st conference on Computing frontiers
Energy-aware deterministic fault tolerance in distributed real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
Reliability-Aware Co-Synthesis for Embedded Systems
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
A Dependability-Driven System-Level Design Approach for Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reliability-Centric High-Level Synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication
DELTA '06 Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications
A Solution to Single Point of Failure Using Voter Replication and Disagreement Detection
DASC '06 Proceedings of the 2nd IEEE International Symposium on Dependable, Autonomic and Secure Computing
Interactive presentation: Reliability-aware system synthesis
Proceedings of the conference on Design, automation and test in Europe
A SystemC-based design methodology for digital signal processing systems
EURASIP Journal on Embedded Systems
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Reliable multiprocessor system-on-chip synthesis
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Efficient symbolic multi-objective design space exploration
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Scheduling of fault-tolerant embedded systems with soft and hard timing constraints
Proceedings of the conference on Design, automation and test in Europe
Specification and design considerations for reliable embedded systems
Proceedings of the conference on Design, automation and test in Europe
On the Evolutionary Optimization of Many Conflicting Objectives
IEEE Transactions on Evolutionary Computation
Combined architecture and hardening techniques exploration for reliable embedded system design
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Symbolic system level reliability analysis
Proceedings of the International Conference on Computer-Aided Design
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This paper presents a system synthesis approach for dependable embedded systems. The proposed approach significantly extends previous work by automatically inserting fault detection and fault toleration mechanisms into an implementation. The main contributions of this paper are 1) a dependability-aware system synthesis approach that automatically performs a redundant task binding and placement of voting structures to increase both, reliability and safety, respectively, 2) an efficient dependability analysis approach to evaluate lifetime reliability and safety, and 3) results from synthesizing a Motion-JPEG decoder for an FPGA platform using the proposed system synthesis approach. As a result, a set of high-quality solutions of the decoder with maximized reliability, safety, performance, and simultaneously minimized resource requirements is achieved.