The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets

Authors:
Michael Wirthlin;Eric Johnson;Nathan Rollins;Michael Caffrey;Paul Graham
Affiliations:
-;-;-;-;-
Venue:
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2003

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Abstract

FPGAs are an appealing solution for space-based remote sensing applications. However, in a low-earthorbit, FPGAs are susceptible to Single-Event Upsets(SEUs). In an effort to understand the effects of SEUs,an SEU simulator based on the SLAAC-1V computing board has been developed. This simulator artifically upsets the configuration memory of an FPGA andmeasures its impact on FPGA designs. The accuracyof this simulation environment has been verified usingground-based radiation testing. This simulation tool isbeing used to characterize the reliability of SEU mitigation techniques for FPGAs.