VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Soft error rate estimation and mitigation for SRAM-based FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Toward Increasing FPGA Lifetime
IEEE Transactions on Dependable and Secure Computing
Torc: towards an open-source tool flow
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs
IEEE Transactions on Computers
Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices
FCCM '13 Proceedings of the 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines
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Today's SRAM-based FPGAs provide a reach set of computing resources which makes them attractive in demanding and critical application domains, such as avionics and space. Unfortunately, their high reliance on SRAM configuration memory arise reliability issues due to the single-event upsets (SEUs). Considering the criticality of these applications, the vulnerability analysis of FPGA designs to SEUs becomes essential part of the design flow. In this context, we present an open-source framework for the soft error vulnerability analysis of Xilinx FPGA devices. The proposed framework will allow researchers to evaluate their reliability-aware CAD algorithms and estimate the soft error susceptibility of the designs at early stages of the implementation flow for the latest Xilinx architectures.