Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Fault Injection for Dependability Validation: A Methodology and Some Applications
IEEE Transactions on Software Engineering
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Experimental analysis of computer system dependability
Fault-tolerant computer system design
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Fault Injection in VHDL Descriptions and Emulation
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
Fault Grading FPGA Interconnect Test Configurations
ITC '02 Proceedings of the 2002 IEEE International Test Conference
An Accurate SER Estimation Method Based on Propagation Probability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Single-event-upset (SEU) awareness in FPGA routing
Proceedings of the 44th annual Design Automation Conference
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Device and architecture concurrent optimization for FPGA transient soft error rate
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory Sharing Approach for TMR Softcore Processor
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
Mitigation of soft errors in SRAM-based FPGAs using CAD tools
Computers and Electrical Engineering
On power and fault-tolerance optimization in FPGA physical synthesis
Proceedings of the International Conference on Computer-Aided Design
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs
Journal of Electronic Testing: Theory and Applications
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
A soft error vulnerability analysis framework for Xilinx FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Previous techniques on FPGA SER estimation are based on time-consuming fault injection and simulation methods.In this paper, we present an analytical approach to estimate the failure rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than fault injection method while is very accurate. We also present a high-reliable low-cost mitigation technique which can significantly improve the availability of FPGA-based designs. This technique is able to tolerate SEUs in both user and configuration bits of mapped designs.