Mixing buffers and pass transistors in FPGA routing architectures
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Proceedings of the IEEE International Test Conference 2001
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Soft error rate estimation and mitigation for SRAM-based FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Improving soft-error tolerance of FPGA configuration bits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
IEEE Transactions on Computers
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
SEU-aware resource binding for modular redundancy based designs on FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Robust discrete synthesis against unspecified disturbances
Proceedings of the 14th international conference on Hybrid systems: computation and control
Mitigation of soft errors in SRAM-based FPGAs using CAD tools
Computers and Electrical Engineering
Mitigating FPGA interconnect soft errors by in-place LUT inversion
Proceedings of the International Conference on Computer-Aided Design
On power and fault-tolerance optimization in FPGA physical synthesis
Proceedings of the International Conference on Computer-Aided Design
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A theory of robust omega-regular software synthesis
ACM Transactions on Embedded Computing Systems (TECS)
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The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with comparable delay. In addition, in Asymmetric SRAM FPGA using our router average FIT (failure-in-time) rate is reduced by 36%.