Low-leakage asymmetric-cell SRAM
Proceedings of the 2002 international symposium on Low power electronics and design
Analyzing Soft Errors in Leakage Optimized SRAM Design
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA
Proceedings of the conference on Design, automation and test in Europe
Single-event-upset (SEU) awareness in FPGA routing
Proceedings of the 44th annual Design Automation Conference
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes
Microelectronics Journal
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
Mitigation of soft errors in SRAM-based FPGAs using CAD tools
Computers and Electrical Engineering
Proceedings of the Conference on Design, Automation and Test in Europe
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms
Journal of Electronic Testing: Theory and Applications
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Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it important to increase their immunity to soft errors. In this work, we propose the use of an asymmetric SRAM (ASRAM) structure that is optimized for soft error immunity and leakage when storing a preferred value. The key to our approach is the observation that the configuration bitstream is composed of 87% of zeros across different designs. Consequently, the use of ASRAM cell optimized for storing a zero (ASRAM-0) reduces the failure in time by 25% as compared to the original design. We also present an optimization that increases the number of zeros in the bitstream while preserving the functionality.