Multiple Errors Produced by Single Upsets in FPGA Configuration Memory: A Possible Solution
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Improving soft-error tolerance of FPGA configuration bits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems
Proceedings of the International Conference on Computer-Aided Design
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This paper proposes a method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of an application circuit to a coarse-grained reconfigurable architecture (CGRA). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the features and parameters of each node in the DFG which characterize impact of the SEU in the node to the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.