Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Analytical Framework for Switch Block Design
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
Fault Grading FPGA Interconnect Test Configurations
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
IEEE Design & Test
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Soft Error Mitigation for SRAM-Based FPGAs
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Improving soft-error tolerance of FPGA configuration bits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAs
DFT '10 Proceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems
Statistical Analysis and Design of HARP FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
Hi-index | 0.00 |
This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft errors. In this switch box architecture, the number of SRAM bits required for programming the switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated on several MCNC benchmarks using the VPR tool. Experimental results show that this architecture decreases the susceptibility of switch boxes to SEUs by about 20% on average compared to the traditional ones.