Soft error rate estimation and mitigation for SRAM-based FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA
Proceedings of the conference on Design, automation and test in Europe
A genetic representation for evolutionary fault recovery in Virtex FPGAs
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes
Microelectronics Journal
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Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconnects. Compared to conventional methods, our technique is orders of magnitude faster, while is able to report all detectable and undetectable faults.