A Comparison of Dynamic Fitness Schedules for Evolutionary Design of Amplifiers
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
GeneticFPGA: Evolving Stable Circuits on Mainstream FPGA Devices
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Fault Grading FPGA Interconnect Test Configurations
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Bridging The Genotype-Phenotype Mapping For Digital Fpgas
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Evolving Messy Gates For Fault Tolerance: Some Preliminary Findings
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Evolved fault tolerance in evolvable hardware
CEC '02 Proceedings of the Evolutionary Computation on 2002. CEC '02. Proceedings of the 2002 Congress - Volume 02
Proceedings of the 3rd conference on Computing frontiers
A combinatorial group testing method for FPGA fault location
ACST'06 Proceedings of the 2nd IASTED international conference on Advances in computer science and technology
Evolutionary functional recovery in virtual reconfigurable circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Evolution of synthetic RTL benchmark circuits with predefined testability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Challenges of evolvable hardware: past, present and the path to a promising future
Genetic Programming and Evolvable Machines
Consensus-Based evaluation for fault isolation and on-line evolutionary regeneration
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
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Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of transistors in a typical FPGA are dedicated to interconnect, nearly 80% according to one estimate, evolutionary fault-recovery systems should benefit by accommodating routing. In this paper, we propose an evolutionary fault-recovery system employing a genetic representation that takes into account both logic and routing configurations. Experiments were run using a software model of the Xilinx Virtex FPGA. We report that using four Virtex combinational logic blocks, we were able to evolve a 100% accurate quadrature decoder finite state machine in the presence of a stuck-at-zero fault.