A combinatorial group testing method for FPGA fault location

Authors:
Carthik A. Sharma;Ronald F. DeMara
Affiliations:
Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL;Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL
Venue:
ACST'06 Proceedings of the 2nd IASTED international conference on Advances in computer science and technology
Year:
2006

Citing 7
Cited 2

Reliable computer systems (2nd ed.): design and evaluation

Reliable computer systems (2nd ed.): design and evaluation
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Scrubbing Away Transients and Jiggling Around the Permanent: Long Survival of FPGA Systems Through Evolutionary Self-Repair

IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Combinatorial group testing methods for the BIST diagnosis problem

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Autonomous FPGA Fault Handling through Competitive Runtime Reconfiguration

EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
A genetic representation for evolutionary fault recovery in Virtex FPGAs

ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Logic synthesis of multilevel circuits with concurrent error detection

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Design of Intelligent PID Controller Based on Adaptive Genetic Algorithm and Implementation of FPGA

ISNN '08 Proceedings of the 5th international symposium on Neural Networks: Advances in Neural Networks, Part II
Autonomic fault-handling and refurbishment using throughput-driven assessment

Applied Soft Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Adaptive fault isolation methods based on discrepancy-enabled pairwise comparisons are developed for reconfigurable logic devices. By observing the discrepancy characteristics of multiple Concurrent Error Detection (CED) configurations, fault isolation is realized without requiring additional test vectors or data coding schemes. Hence the reprogrammability of Field Programmable Gate Arrays (FPGAs) is utilized to examine CED alternatives in succession. Results show that for a reprogrammable device with one million resources, where 50% of the resources are used on an average by the target application, fault isolation can be achieved in as few as 28 iterations. The effect of resource utilization, the number of competing candidate solutions, and the number of unit resources are analyzed and the performance of a halving-based algorithm for fault isolation are quantified.