Modifications of Competitive Group Testing
SIAM Journal on Computing
A new competitive algorithm for group testing
Discrete Applied Mathematics
Test and diagnosis of fault logic blocks in FPGAs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Salvaging Test Windows in BIST Diagnostics
IEEE Transactions on Computers
Improved fault diagnosis in scan-based BIST via superposition
Proceedings of the 37th Annual Design Automation Conference
BIST-based test and diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fault Diagnosis in Scan-Based BIST
Proceedings of the IEEE International Test Conference
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A combinatorial group testing method for FPGA fault location
ACST'06 Proceedings of the 2nd IASTED international conference on Advances in computer science and technology
Embedded fault diagnosis in digital systems with BIST
Microprocessors & Microsystems
A survey of combinatorial testing
ACM Computing Surveys (CSUR)
The Minimal Failure-Causing Schema of Combinatorial Testing
ACM Transactions on Software Engineering and Methodology (TOSEM)
Constraint-Based approaches to the covering test problem
CSCLP'04 Proceedings of the 2004 joint ERCIM/CoLOGNET international conference on Recent Advances in Constraints
Self-healing reconfigurable logic using autonomous group testing
Microprocessors & Microsystems
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We examine an abstract formulation of BIST diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vectors, faulty scan cells, faulty modules, and faulty logic blocks in FPGAs. We develop an abstract model of this problem and show a fundamental correspondence to the well-established subject of Combinatorial Group Testing (CGT) [7]. Armed with this new perspective, we show how to improve on a number of existing techniques in the VLSI diagnosis literature. In addition, we adapt and apply a number of CGT algorithms that are well-suited to the diagnosis problem in the digital realm. We also propose completely new methods and empirically evaluate the different algorithms. Our experiments show that results of the proposed algorithms outperform recent diagnosis techniques [8, 9, 14]. Finally, we point out future directions that can lead to new solutions for the BIST diagnosis problem.