Low overhead fault-tolerant FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
BIST-Based Diagnostics of FPGA Logic Blocks
Proceedings of the IEEE International Test Conference
A Novel Fault Tolerant Approach for SRAM-Based FPGAs
PRDC '99 Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Asteroid Exploration with Autonomic Systems
ECBS '04 Proceedings of the 11th IEEE International Conference and Workshop on Engineering of Computer-Based Systems
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Combinatorial group testing methods for the BIST diagnosis problem
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Column-Based Precompiled Configuration Techniques for FPGA
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
From Reconfigurable Architectures to Self-Adaptive Autonomic Systems
CSE '09 Proceedings of the 2009 International Conference on Computational Science and Engineering - Volume 02
New and improved BIST diagnosis methods from combinatorial Group testing theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A group-testing-based fault resolution is incorporated into SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) to provide an evolvable hardware system with self-healing and self-organizing properties. The proposed approach employs adaptive group testing techniques to autonomously maintain FPGA resource viability information as an organic means of transient and permanent fault resolution. Reconfigurability of the SRAM-based FPGA is leveraged to locate faulty logic resources which are successively excluded by group testing using alternate device configurations. This simplifies the system architect's role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance vs. availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an observer-controller model. The proposed group testing method operates on the output response produced for real-time operational inputs, which eliminates the need for dedicated test vectors. The proposed system was demonstrated using a Data Encryption Standard (DES) core on 4-input and 6-input LUT-based Xilinx FPGA models. With a single simulated stuck-at fault, the system identifies a completely validated replacement configuration within a few test stages. Results also include approaches for optimizing group size, resource redundancy, and availability. The approach demonstrates a readily-implemented yet robust organic hardware application that features a high degree of autonomous self-control.