Analysis and Detection of Timing Failures in an Experimental Test Chip
Proceedings of the IEEE International Test Conference on Test and Design Validity
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Quality and Single-Stuck Faults
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
CMOS IC reliability indicators and burn-in economics
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Quantitative analysis of very-low-voltage testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
The Effectiveness of IDDQ and High Voltage Stress for Burn-in Elimination
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Design Diversity Metric and Analysis of Redundant Systems
IEEE Transactions on Computers
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System
Journal of Electronic Testing: Theory and Applications
Techniques for Estimation of Design Diversity for Combinational Logic Circuits
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
ITC '00 Proceedings of the 2000 IEEE International Test Conference
COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
WHY DEFECTS ESCAPE SOME OF OUR TESTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiple-Output Propagation Transition Fault Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing for Resistive Opens and Stuck Opens
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Defects and Faults in Quantum Cellular Automata at Nano Scale
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Delay Defect Screening using Process Monitor Structures
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
ELF-Murphy Data on Defects and Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Efficient Design Diversity Estimation for Combinational Circuits
IEEE Transactions on Computers
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Test chip experimental results on high-level structural test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BUSpec: A framework for generation of verification aids for standard bus protocol specifications
Integration, the VLSI Journal
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On bridging simulation and formal verification
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Fault modeling for FinFET circuits
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Generation of compact test sets with high defect coverage
Proceedings of the Conference on Design, Automation and Test in Europe
Fault Models for Quantum Mechanical Switching Networks
Journal of Electronic Testing: Theory and Applications
Diagnosis of single stuck-at faults and multiple timing faults in scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits
Journal of Electronic Testing: Theory and Applications
Self-healing reconfigurable logic using autonomous group testing
Microprocessors & Microsystems
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Quantitative evaluation of soft error injection techniques for robust system design
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.01 |
This paper studies some manufacturing test datacollected for an experimental digital IC. Test resultsfor a large variety of single-stuck fault based test setsare shown and compared with a number of test setsbased on other fault models. The defects present in thechips studied are characterized based on the chip testerresponses. The data presented shows that N-detect testsets are particularly effective for both timing and hardfailures. In these test sets each single-stuck fault isdetected by at least N different test patterns.We also present data on the use of IDDq tests andVLV (very low voltage) tests for detecting defects whosepresence doesn't interfere with normal operationduring manufacturing test, but which cause early lifefailure.