Analysis and Detection of Timing Failures in an Experimental Test Chip

Testability Features of the AMD-K6 Microprocessor

IEEE Design & Test

Delay test of chip I/Os using LSSD boundary scan

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Analysis of pattern-dependent and timing-dependent failures in an experimental test chip

ITC '98 Proceedings of the 1998 IEEE International Test Conference

An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

6.3 Experimental Results for IDDQ and VLV Testing

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Stuck-Fault Tests vs. Actual Defects

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Multiple-Output Propagation Transition Fault Test

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Testability Features of AMD-K6" Microprocessor

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs

IEEE Transactions on Computers