An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Analysis and Detection of Timing Failures in an Experimental Test Chip
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Comparison of Defect Models for Fault Location with IDDQ Measurements
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
An efficient CMOS bridging fault simulator: with SPICE accuracy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
This paper describes the testability featuresand test pattern development methodologies forthe AMD-K6驴 Microprocessor. The embeddedDesign for Testability (DFT) structures andtest strategy provide high quality manufacturingtests.