Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning
IEEE Transactions on Computers
Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ
Journal of Electronic Testing: Theory and Applications
Testability Features of the AMD-K6 Microprocessor
IEEE Design & Test
Defect level prediction for I_DDQ testing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Transistor leakage fault location with ZDDQ measurement
ATS '95 Proceedings of the 4th Asian Test Symposium
A simple technique for locating gate-level faults in combinational circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Correlation between I/sub DDQ/ testing quality and sensor accuracy
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Synthesis of I/sub DDQ/-testable circuits: integrating built-in current sensors
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Defect Detection from Visual abnormalities in Manufacturing Process Using IDDQ
ETW '00 Proceedings of the IEEE European Test Workshop
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Testability Features of AMD-K6" Microprocessor
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Signature Analysis for IC Diagnosis and Failure Analysis
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Current Signatures: Application
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Fault Diagnosis and Fault Model Aliasing
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Journal of Electronic Testing: Theory and Applications
Selection of a fault model for fault diagnosis based on unique responses
Proceedings of the Conference on Design, Automation and Test in Europe
Selection of a fault model for fault diagnosis based on unique responses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step
Proceedings of the Conference on Design, Automation and Test in Europe
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