An evolution-based approach to partitioning ASIC systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Proportional BIC sensor for current testing
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Design of ICs applying built-in current testing
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Numerical Optimization of Computer Models
Numerical Optimization of Computer Models
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Comparison of Defect Models for Fault Location with IDDQ Measurements
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Simulation Results of an Efficient Defect-Analysis Procedure
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Incorporating I_DDQ Testing with BIST forImproved Coverage: An Experimental Study
Journal of Electronic Testing: Theory and Applications
Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based Design
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Compact Built-In Current Sensor for IDDQ Testing
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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"On-Chip" I/sub DDQ/ testing by the incorporation of Built-In Current (BIC) sensors has some advantages over "off-chip" techniques. However, the integration of sensors poses analog design problems which are hard to solve for a digital designer. The automatic incorporation of the sensors using parameterized BIC cells could be a promising alternative. The work reported here identifies partitioning criteria to guide the synthesis of I/sub DDQ/-testable circuits. The circuit must be partitioned, such that the defective I/sub DDQ/ is observable, and the power supply voltage perturbation is within specified limits. In addition to these constraints, cost criteria are considered: circuit extra delay, area overhead of the BIC sensors, connectivity costs of the test circuitry, and the test application time. The parameters are estimated based on logical as well as electrical level information of the target cell library to be used in the technology mapping phase of the synthesis process. The resulting cost function is optimized by an evolution-based algorithm. When run over large benchmark circuits our method gives significantly superior results to those obtained using simpler and less comprehensive partitioning methods.