Artificial Intelligence and the Design of Expert Systems
Artificial Intelligence and the Design of Expert Systems
IC Failure Analysis: Magic, Mystery, and Science
IEEE Design & Test
Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Comparison of Defect Models for Fault Location with IDDQ Measurements
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
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A method of signature analysis is presented that is basedon ATE data, experiential knowledge of failure modes andmechanisms, or a combination of both. This method canbe used on low numbers of failures or even single failures.It uses the Dempster-Shafer theory to calculate failuremechanism confidence. This method can be used for rapiddiagnosis of complex IC failures, as illustrated by thedefect shown in Fig. 1. The model is developed and anexample is given based on Sandia's 0.5 mm CMOS ICtechnology.