Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
A Comparison of Defect Models for Fault Location with IDDQ Measurements
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Built-In Current Sensor for IDDQ Test in CMOS
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A built-in quiescent current monitor for CMOS VLSI circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Iddq Testing for High Performance CMOS - The Next Ten Years
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Deep Sub-Micron IDDQ Testing: Issues and Solutions
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Compact Built-In Current Sensor for IDDQ Testing
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scalable power control for many-core architectures running multi-threaded applications
Proceedings of the 38th annual international symposium on Computer architecture
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This paper describes results on Built-In Current Sensors destined to overcome the limitations of IDDQ testing in deep submicron circuits. The problems of performance penalty, test accuracy and test speed are addressed. A new sensor composed of a source-controlled comparator operating at low supply voltages and bias currents is used. Gradual sensor activation ensures reliable low noise operation. It is combined with large bypass MOS switches avoiding performance penalty, as well as a second bypass and compensation logic to increase test speed.