Fundamentals of MOS digital integrated circuits
Fundamentals of MOS digital integrated circuits
IDDQ testing in CMOS digital ASICs
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
CMOS scaling into the 21st century: 0.1 &mgr;m and beyond
IBM Journal of Research and Development - Special issue: IBM CMOS technology
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
IC test using the energy consumption ratio
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Deep submicron defect detection with the energy consumption ratio
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
IDDQ Testing of Submicron CMOS—by Cooling?
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Bridging Faults in Pipelined Circuits
Journal of Electronic Testing: Theory and Applications
Estimation of the defective IDDQ caused by shorts in deep-submicron CMOS ICs
Proceedings of the conference on Design, automation and test in Europe
LEAP: An Accurate Defect-Free IDDQ Estimator
Journal of Electronic Testing: Theory and Applications
IDDQ Testing: Issues Present and Future
IEEE Design & Test
Deep Sub-Micron IDDQ Testing: Issues and Solutions
EDTC '97 Proceedings of the 1997 European conference on Design and Test
LEAP: An Accurate Defect-Free IDDQ Estimator
ETW '00 Proceedings of the IEEE European Test Workshop
Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An Analysis of the Delay Defect Detection Capability of the ECR Test Method
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
IDDQ Characterization in Submicron CMOS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
BART: A Bridging Fault Test Generator for Sequential Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
Data remanence in semiconductor devices
SSYM'01 Proceedings of the 10th conference on USENIX Security Symposium - Volume 10
Data remanence in semiconductor devices
SSYM'01 Proceedings of the 10th conference on USENIX Security Symposium - Volume 10
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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CMOS scaling affects the subthreshold current per IC, and it directly impacts the utility of Iddq testing for CMOS devices. Continued IC manufacturing refinements enable a factor of 2**(1/2) reduction in line widths every three years. This in conjunction with an increase in chip size makes it possible to increase the number of transistors per IC by a factor between two and three. This trend in CMOS technology is expected to continue over at least the next ten years. The scaling of devices affects numerous device parameters, one being the subthreshold current commonly known as the leakage current. Assuming defect size scales with technology, it will be explained why it will become increasingly difficult to differentiate good and defective devices based upon an Iddq test methodology.