IDDQ testing as a component of a test suite: the need for several fault coverage metrics
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Quiescent current analysis and experimentation of defective CMOS circuits
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Design of ICs applying built-in current testing
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Separate IDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis
Journal of Electronic Testing: Theory and Applications
Identifying defects in deep-submicron CMOS ICs
IEEE Spectrum
Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
On the Effect of ISSQ Testing in Reducing Early Failure Rate
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
High Resolution IDDQ Characterization and Testing - Practical Issues
Proceedings of the IEEE International Test Conference on Test and Design Validity
Burn-in Elimination of a High Volume Microprocessor Using IDDQ
Proceedings of the IEEE International Test Conference on Test and Design Validity
Stuck Fault and Current Testing Comparison Using CMOS Chip Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Is IDDQ Yield Loss Inevitable?
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Iddq Testing for High Performance CMOS - The Next Ten Years
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Feasibility of Employing and IDDQ Output Amplifier in Deep Submicron Built-in Current Sensors
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
Viewpoint: Dealing With Yield Losses in Iddq Testing
IEEE Spectrum
Differential Thermal Testing: An Approach to its Feasibility
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Influence of manufacturing variations in IDDQ measurements: a new test criterion
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Analog Integrated Circuits and Signal Processing
On effective IDDQ Testing of low-voltage CMOS circuits using leakage control techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IC Failure Analysis: Magic, Mystery, and Science
IEEE Design & Test
IEEE Design & Test
Fault Detection and Location Using IDD Waveform Analysis
IEEE Design & Test
IDDQ Test: Will It Survive the DSM Challenge?
IEEE Design & Test
CMOS IC reliability indicators and burn-in economics
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Analysis of the Delay Defect Detection Capability of the ECR Test Method
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Experiences with Implementation of IDDQ Test for Identification and Automotive Products
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Compact Built-In Current Sensor for IDDQ Testing
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
On Testability of Multiple Precharged Domino Logic
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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IDDQ testing has emerged from a company-specific CMOS IC test technology in the 1960's and 1970's to a worldwide-accepted technique that is a requirement for low-defect PPM levels and failure rates. It is the single most sensitive test method to detect CMOS IC defects and an abundance of studies have laid a solid foundation for why this is so.The IDDQ test uses the quiescent power supply current of logic states as an indication of defect presence. Its major requirement for maximum efficiency is that the design implement nanowatt power levels (nanoamp supply current) in the quiescent portion of the power supply current. No direct connections are allowed between VDD and VSS during the quiescent period.IDDQ testing has increased significantly since 1990, highlighting problems and driving solutions not addressed by the high reliability manufacturers of earlier technologies. Faster IDDQ instrumentation and better software tools to generate and grade IDDQ test patterns are a result of this increased interest. Two major issues confronting IDDQ testing are addressed: the yield loss issue and increased background current of deep submicron IC technologies projected by the SIA/Sematech road map. Both issues are points of controversy.