Design of ICs applying built-in current testing
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Separate IDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis
Journal of Electronic Testing: Theory and Applications
Introduction to IDDQ testing
Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IDDQ Test and Diagnosis of CMOS Circuits
IEEE Design & Test
IDDQ Testing: Issues Present and Future
IEEE Design & Test
On Test Generation for Iddq Testing of Bridging Faults in CMOS Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
IC Defects-Based Testability Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
DFT for Delay Fault Testing of High-Performance Digital Circuits
IEEE Design & Test
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The use of low threshold devices in low voltage CMOS circuits leads to an exponential increase in the intrinsic leakage current. This threatens the effectiveness of IDDQ testing for such low voltage circuits because it is difficult to differentiate a defect-free circuit from defective circuits. Recently, several leakage control techniques have been proposed to reduce intrinsic leakage current, which may benefit IDDQ testing. In this paper we investigate the possibilities of applying different leakage control techniques to improve the fault coverage of IDDQ testing. Results on a large number of benchmarks indicate that dual threshold and vector control techniques are very effective in improving fault coverage for IDDQ testing.