Compaction of IDDQ Test Sequence Using Reassignment Method
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Fault models and test generation for IDDQ testing: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
On effective IDDQ Testing of low-voltage CMOS circuits using leakage control techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
6.2 A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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An efficient automatic test pattern generator for I/sub DDQ/ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. An adaptive genetic algorithm (GA) is used to generate compact test sets. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented. The results show that GA-based test generators are very well suited for generating compact test sets for I/sub DDQ/ testing of bridging faults.