Introduction to IDDQ testing

IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays

IEEE Transactions on Computers

A Low-Loss Built-In Current Sensor

Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop

Nanometer Technology Effects on Fault Models for IC Testing

Computer

Fault models and test generation for IDDQ testing: embedded tutorial

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

On effective IDDQ Testing of low-voltage CMOS circuits using leakage control techniques

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Configurations for IDDQ-Testable PLAs

IEEE Design & Test

System-on-Chip Testability Using LSSD Scan Structures

IEEE Design & Test

Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing

Journal of Electronic Testing: Theory and Applications

Divide-and-Conquer IDDQ Testing for Core-based System Chips

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

An Analysis of the Delay Defect Detection Capability of the ECR Test Method

ITC '00 Proceedings of the 2000 IEEE International Test Conference

On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)

FPGA Bridging Fault Detection and Location via Differential I{DDQ}

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Graphical IDDQ signatures reduce defect level and yield loss

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Polynomial coefficient based DC testing of non-linear analog circuits

Proceedings of the 19th ACM Great Lakes symposium on VLSI