Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
Test methodologies and design automation for IBM ASICs
IBM Journal of Research and Development
Introduction to IDDQ testing
Technology adaption in logic synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Introducing Core-Based System Design
IEEE Design & Test
Core Design and System-on-a-Chip Integration
IEEE Design & Test
A Design For Test Perspective on I/O Management
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor Subsystem
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Addressing Early Design-For-Test Synthesis in a Production Environment
Proceedings of the IEEE International Test Conference
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Core test connectivity, communication, and control
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design of an Efficient Weighted-Random-Pattern Generation System
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
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A technology-independent test synthesis tool extends the basic level-sensitive scan design (LSSD) boundary scan methodology. It reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.