The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
System-on-Chip Testability Using LSSD Scan Structures
IEEE Design & Test
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip
Integration, the VLSI Journal
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper describes work at TI on a scan testarchitecture that provides test connectivity,communication, and control of embedded cores withinsystem ICs. Low power scan testing and hierarchicalreuse are also provided by the test architecture.