MCM Test Strategy Synthesis from Chip Test and Board TestApproaches
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
A Formalization of the IEEE 1149.1-1990 DiagnosticMethodology as Applied to Multichip Modules
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Multichip Module Diagnosis by Product-Code Signatures
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
IEEE Transactions on Computers
A Dependable High Performance Wafer Scale Architecture for Embedded Signal Processing
IEEE Transactions on Computers
Thermal Monitoring of Self-Checking Systems
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Journal of Electronic Testing: Theory and Applications
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
A digital partial built-in self-test structure for a high performance automatic gain control circuit
DATE '99 Proceedings of the conference on Design, automation and test in Europe
ICEBERG: an embedded in-circuit emulator synthesizer for microcontrollers
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
From DFT to systems test - a model based cost optimization tool
Proceedings of the conference on Design, automation and test in Europe
Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures
IEEE Transactions on Computers
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
Journal of Electronic Testing: Theory and Applications
Adaptive Fault Detection and Diagnosis of RAM Interconnects
Journal of Electronic Testing: Theory and Applications
A Rapid-Prototyping Environment for Digital-Signal Processors
IEEE Design & Test
Fault Isolation in an Integrated Diagnostic Environment
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Design for Testability in Hardware-Software Systems
IEEE Design & Test
A D&T Special Report: P1149.4 Mixed-Signal Test Bus
IEEE Design & Test
Designing UltraSparc for Testability
IEEE Design & Test
Alpha 21164 Testability Strategy
IEEE Design & Test
IEEE Design & Test
The Power PC 601 Microprocessor
IEEE Micro
Considering Workload Input Variations in Error Coverage Estimation
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Generating interconnect models from prototype hardware
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On-line testing of scalable signal processing architectures using a software test method
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Core test connectivity, communication, and control
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Exploitation of parallelism in group probing for testing massively parallel processing systems
ATS '95 Proceedings of the 4th Asian Test Symposium
Mixed-signal circuits and boards for high safety applications
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Thumb: Reducing the Cost of 32-bit RISC Performance in Portable and Consumer Applications
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Strategies and Structures for Test Access in Mixed-Signal MCMs
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
A supercomputer system interconnect and scalable IOS
MSS '95 Proceedings of the 14th IEEE Symposium on Mass Storage Systems
17.2 A Design for Testability Study on a High Performance Automatic Gain Control Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
End-to-End Testing for Boards and Systems Using Boundary Scan
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Methodology for the McKinley Processor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
CTL the Language for Describing Core-Based Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test and Debug Strategy of the PNX8525 Nexperia" Digital Video Platform System Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Configuration Free SoC Interconnect BIST Methodology
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Enhanced Reduced Pin-Count Test for Full-Scan Design
ITC '01 Proceedings of the 2001 IEEE International Test Conference
BIST and Fault Insertion Re-use in Telecom Systems
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Parameterized VHDL Library for On-Line Testing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
BIST-Based Diagnostics of FPGA Logic Blocks
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ITC '97 Proceedings of the 1997 IEEE International Test Conference
desire to reduce (or eliminate) complex and in P1149.4 Environment
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testing the Enterprise IBM System/390" Multi Processor
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Improving On-Line BIST-Based Diagnosis for Roving STARs
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
System Design Verification Tests - An Overview
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Re-configurable embedded core test protocol
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Project Kittyhawk: building a global-scale computer: Blue Gene/P as a generic computing platform
ACM SIGOPS Operating Systems Review
An novel methodology for reducing SoC test data volume on FPGA-based testers
Proceedings of the conference on Design, automation and test in Europe
IEEE standard 1500 compliance verification for embedded cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
microSPARCTM: a case-study of scan based debug
ITC'94 Proceedings of the 1994 international conference on Test
3B21D BIST/boundary-scan system diagnostic test story
ITC'94 Proceedings of the 1994 international conference on Test
Modeling for structured system interconnect test
ITC'94 Proceedings of the 1994 international conference on Test
System-level testability of hardware/software systems
ITC'94 Proceedings of the 1994 international conference on Test
A generic test and maintenance node for embedded system test
ITC'94 Proceedings of the 1994 international conference on Test
A serially addressable, flexible current monitor for test fixture based IDDQ/ISSQtesting
ITC'94 Proceedings of the 1994 international conference on Test
Built-in system test and fault location
ITC'94 Proceedings of the 1994 international conference on Test
ITC'94 Proceedings of the 1994 international conference on Test
Environmental stress testing with boundary-scan
ITC'94 Proceedings of the 1994 international conference on Test
An approach to accelerate scan testing in IEEE 1149.1 architectures
ITC'94 Proceedings of the 1994 international conference on Test
Test strategies for a family of complex MCMs
ITC'94 Proceedings of the 1994 international conference on Test
An IDDQ based built-in concurrent test technique for interconnects in a boundary scan environment
ITC'94 Proceedings of the 1994 international conference on Test
Goal-directed vector generation using sample ICs
ITC'94 Proceedings of the 1994 international conference on Test
Do you practice safe test? what we found out about your habits
ITC'94 Proceedings of the 1994 international conference on Test
Structure and metrology for a single-wire analog testability bus
ITC'94 Proceedings of the 1994 international conference on Test
ΔΣ modulation based on-chip ramp generator for ADC BIST
CONTROL'05 Proceedings of the 2005 WSEAS international conference on Dynamical systems and control
FPGA & DSP infrared image processing module for people and objects detection
Proceedings of the 15th WSEAS international conference on Systems
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