System-level fault diagnosis: A survey
Microprocessing and Microprogramming - Fault tolerant computing
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Built-In Testing of Integrated Circuit Wafers
IEEE Transactions on Computers
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
Almost Sure Diagnosis of Almost Every Good Element
IEEE Transactions on Computers
| Hi-index | 14.98 |
A boundary scan-based algorithm is presented for testing iterative arrays of identical units such as integrated circuits on silicon wafers, MCMs fabricated on a large area panel, and multiprocessor systems. As all the units are similar, it is critical that the test process be parallelized in order that multiple units may be tested for the cost of testing one unit. With this objective in mind, we propose a parallel and pipelined Boundary Scan Standard-based scheme for testing all units simultaneously. In this scheme, the test vectors and the corresponding correct-response vectors are both scanned into the scan chain of the units in an interleaved fashion, optimally utilizing the resources of every chain to test all units. The comparison of the expected versus the observed response of a unit is performed locally at each unit. Our algorithm provides an order of magnitude speed-up in test time over conventional boundary scan based testing schemes. Further, as the number of chains increases, the test time tends asymptotically toward the optimal. The complete design of the test architecture is also presented in the paper.