Strongly Code Disjoint Checkers
IEEE Transactions on Computers
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
On the Design of Self-Checking Boundary Scannable Boards
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
The Timely Computing Base Model and Architecture
IEEE Transactions on Computers
Availability Requirement for a Fault Management Server in High-Availability Communication Systems
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Fault-tolerant systems with concurrent error-locating capability
Journal of Computer Science and Technology
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
Proceedings of the 1st conference on Computing frontiers
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
IEEE Design & Test
Towards policy-based system on privacy
ISP'06 Proceedings of the 5th WSEAS International Conference on Information Security and Privacy
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This paper describes a fault-tolerant system that is based on two replicas of a self-checking module and on an error-masking interface. The main contributions of this work rely on the fail-safe/strongly-fail-safe design of the error-masking interface, and on the analysis of the competitiveness of this fault-tolerant scheme with respect to its reliability.