Designing Fault-Tolerant Techniques for SRAM-Based FPGAs

Authors:
Fernanda Gusmao de Lima Kastensmidt;Gustavo Neuberger;Renato Fernandes Hentschke;Luigi Carro;Ricardo Reis
Affiliations:
State University of Rio Grande do Sul;Federal University of Rio Grande do Sul;Federal University of Rio Grande do Sul;Federal University of Rio Grande do Sul;Federal University of Rio Grande do Sul
Venue:
IEEE Design & Test
Year:
2004

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Abstract

Editors' note: FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuit's operation. This article presents a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CED) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques. 驴Dimitris Gizopoulos, University of Piraeus; and Yervant Zorian, Virage Logic