PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
An FPGA architecture with enhanced datapath functionality
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Design Challenges of Technology Scaling
IEEE Micro
Defect and Fault Tolerance FPGAs by Shifting the Configuration Data
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
The Impact of Technology Scaling on Lifetime Reliability
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
IEEE Design & Test
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Defect-Aware Design Paradigm for Reconfigurable Architectures
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 43rd annual Design Automation Conference
Fault-Tolerant Systems
Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing)
Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing)
Interconnect lifetime prediction for reliability-aware systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Single Event Upset: An Embedded Tutorial
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Reliability Optimization of Reconfigurable Computing-Based Fault-Tolerant System
HPCC '09 Proceedings of the 2009 11th IEEE International Conference on High Performance Computing and Communications
A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems
ATS '09 Proceedings of the 2009 Asian Test Symposium
Maximizing area-constrained partial fault tolerance in reconfigurable logic
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Negative Bias Temperature Instability in CMOS Devices
Microelectronic Engineering
What's cool for the future of ultra low power designs?
Proceedings of the 47th Design Automation Conference
AgeSim: a simulation framework for evaluating the lifetime reliability of processor-based SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
A software framework for dynamic self-repair in embedded SoCs exploiting reconfigurable devices
AQTR '10 Proceedings of the 2010 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR) - Volume 02
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On Supporting Rapid Thermal Analysis
IEEE Computer Architecture Letters
A framework for enabling fault tolerance in reconfigurable architectures
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
A Methodology for Alleviating the Performance Degradation of TMR Solutions
IEEE Embedded Systems Letters
| Hi-index | 0.00 |
Technology scaling, in conjunction to the trend towards higher operation frequency, results in increased thermal stress, which in turn leads to upsets due to reliability degradation. In this paper, we introduce a software-supported framework targeting to enable sufficient fault coverage against upsets occurred due to aging phenomena. Experimental results with a number of industrial oriented DSP kernels shown the effectiveness of our framework, since we achieved average improvement in terms of maximum operation frequency and power consumption by 15% and 70%, respectively, as compared to a well-established commercial solution, for comparable fault masking.