Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Securing netlist-level FPGA design through exploiting process variation and degradation
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
A low-cost fault tolerant solution targeting commercial FPGA devices
Journal of Systems Architecture: the EUROMICRO Journal
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This paper reviews the experimental and modeling efforts to understand the mechanism of Negative Bias Temperature Instability (NBTI) in p-MOSFETs, which is becoming a serious reliability concern for analog and digital CMOS circuits. Conditions for interface and bulk trap generation and their dependence onstress voltage and oxide field, temperature and time are discussed. The role of inversion layer holes, hot-holes and hot-electrons are also discussed. The recovery of generated damage and its bias, temperature and AC frequency dependence are discussed. The degradation and recovery is modeled using the standard Reaction-Diffusion theory, and some unique data scaling features are pointed out. The impact of gate-oxide nitridation is also reviewed.