Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Design For Degradation: CAD Tools for Managing Transistor Degradation Mechanisms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
IMPACT OF NEGATIVE BIAS TEMPERATURE INSTABILITY ON PRODUCT PARAMETRIC DRIFT
ITC '04 Proceedings of the International Test Conference on International Test Conference
Negative Bias Temperature Instability in CMOS Devices
Microelectronic Engineering
I-cache multi-banking and vertical interleaving
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
NBTI-aware flip-flop characterization and design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
NBTI resilient circuits using adaptive body biasing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A framework for estimating NBTI degradation of microarchitectural components
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
NBTI tolerant microarchitecture design in the presence of process variation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
International Journal of Parallel Programming
Skew management of NBTI impacted gated clock trees
Proceedings of the 19th international symposium on Physical design
A multi-level approach to reduce the impact of NBTI on processor functional units
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Aging effects of leakage optimizations for caches
Proceedings of the 20th symposium on Great lakes symposium on VLSI
SRAM-based NBTI/PBTI sensor system design
Proceedings of the 47th Design Automation Conference
Dynamic indexing: concurrent leakage and aging optimization for caches
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Aging-resilient design of pipelined architectures using novel detection and correction circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Proactive NBTI mitigation for busy functional units in out-of-order microprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
A new design-for-test technique for SRAM core-cell stability faults
Proceedings of the Conference on Design, Automation and Test in Europe
Optimal sizing of configurable devices to reduce variability in integrated circuits
Proceedings of the Conference on Design, Automation and Test in Europe
An on-chip NBTI sensor for measuring pMOS threshold voltage degradation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combating Aging with the Colt Duty Cycle Equalizer
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Controlling NBTI degradation during static burn-in testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Buffering of frequent accesses for reduced cache aging
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Leakage power and circuit aging cooptimization by gate replacement techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DEFCAM: A design and evaluation framework for defect-tolerant cache memories
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the 48th Design Automation Conference
MECCA: a robust low-overhead PUF using embedded memory array
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Detecting stability faults in sub-threshold SRAMs
Proceedings of the International Conference on Computer-Aided Design
Alleviating NBTI-induced failure in off-chip output drivers
Proceedings of the great lakes symposium on VLSI
Energy-optimal caches with guaranteed lifetime
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems
Journal of Electronic Testing: Theory and Applications
A novel gate-level NBTI delay degradation model with stacking effect
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
Combating NBTI-induced aging in data caches
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Sensor-wise methodology to face NBTI stress of NoC buffers
Proceedings of the Conference on Design, Automation and Test in Europe
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints
Proceedings of the 50th Annual Design Automation Conference
Enhancing NBTI recovery in SRAM arrays through recovery boosting
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compact degradation sensors for monitoring NBTI and oxide degradation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-specific memory partitioning for joint energy and lifetime optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Low power aging-aware register file design by duty cycle balancing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Use it or lose it: wear-out and lifetime in future chip multiprocessors
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Reliability improvement of logic and clock paths in power-efficient designs
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
Proceedings of the International Conference on Computer-Aided Design
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Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in Static Noise Margin (SNM), which is a measure of the read stability of the 6-T SRAM cell has been estimated using Reaction-Diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique.