Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Cache Design for Low Power and High Yield
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Implementation of low-voltage static RAM with enhanced data stability and circuit speed
Microelectronics Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a new read and write assist technique to enable lower voltage operation for Static Random Access Memory (SRAM). The ability to scale the operating voltage with frequency of the chip has big impact on power consumption (P@av^2). The lower end of the operating voltage (V"d"d"m"i"n) for most chips is determined by the stability of the SRAM cell. The new technique uses a contention-free circuit to generate a Reduced Voltage Swing (RVS) on the wordline (VWL) and selectively reduce the supply to the bitcell (V"d"d"m"e"m) during write. The required VWL and bitcell voltages are programmable and controllable to adapt to performance and yield requirements. An 8KB memory test-chip was designed to demonstrate this technique in a low-leakage 45nm process technology. Results show a 7 to 19% improvement in V"d"d"m"i"n depending on the process corner, which translates into 14-40% reduction on active power. The proposed technique has 4% area overhead and minimal impact to speed.