Characterization of a novel nine-transistor SRAM cell
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel technique to reduce write delay of SRAM architectures
WSEAS Transactions on Circuits and Systems
Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Single-ended, robust 8T SRAM cell for low-voltage operation
Microelectronics Journal
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This paper presents a novel SRAM circuit technique for simultaneously enhancing the cell operating margin and improving the circuit speed in low-voltage operation. During each access, the wordline and cell power node of selected SRAM cells are internally boosted into two different voltage levels. This technique with optimized boosting levels expands the read margin and the write margin to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 256Kbit SRAM test chip with the proposed technique has been fabricated in a 0.18@mm CMOS logic process. For 0.8V supply voltage, the design scheme increases the cell read margin by 76%, the cell write margin by 54% and the cell read-out current by three times at the expense of 14.6% additional active power. Silicon measurement eventually confirms that the proposed SRAM achieves nearly 1.2 orders of magnitude reduction in a die bit-error count while operating with 26% faster speed compared with those of conventional SRAM.