A novel technique to reduce write delay of SRAM architectures

Authors:
Swapnil Vats;R. K. Chauhan
Affiliations:
Department of Electronics and Communication Engineering, M.M.M. Engineering College, Gorakhpur, U.P., India;Department of Electronics and Communication Engineering, M.M.M. Engineering College, Gorakhpur, U.P., India
Venue:
WSEAS Transactions on Circuits and Systems
Year:
2011

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Abstract

This paper presents a novel circuit technique for improving the write delay of an SRAM cell. The technique is common for all the SRAM architecture. It utilizes a PMOS between power supply rail and the SRAM cell and an NMOS between SRAM cell and ground. The simulation results for write delay, SNM and power dissipation were presented with and without application of proposed technique on two different SRAM architectures. Significant improvements on write delay and power dissipation were noticed for the proposed modified SRAM architectures with less impact on SNM.