Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Combating NBTI Degradation via Gate Sizing
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Aging effects of leakage optimizations for caches
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Dynamic indexing: concurrent leakage and aging optimization for caches
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Investigating the impact of NBTI on different power saving cache strategies
Proceedings of the Conference on Design, Automation and Test in Europe
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Proceedings of the Conference on Design, Automation and Test in Europe
Gate replacement techniques for simultaneous leakage and aging optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Previous works have shown that typical power management knobs such as voltage scaling or power gating can also be exploited to reduce aging phenomena caused by Negative Bias Temperature Instability (NBTI). We propose a scheme for power-managed caches that allows to significantly improving the aging of the cache thanks to the use of a small buffer that stores a copy of the lines that are most critical for aging, that is, the ones with the least opportunity of being power-managed; by using the buffer instead of the cache when accessing these critical lines, the original cache is preserved and its lifetime is significantly prolonged. As a side effect, this scheme improves total power since the less energy-hungry buffer is accessed most of the time. Experimental analysis shows this scheme allows to achieve significant (3x on average) lifetime extensions for the cache, with a concurrent energy saving between 18 and 24%, depending on cache size.