Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 43rd annual Design Automation Conference
Electronics beyond nano-scale CMOS
Proceedings of the 43rd annual Design Automation Conference
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
Proceedings of the conference on Design, automation and test in Europe
An algorithm to minimize leakage through simultaneous input vector control and circuit modification
Proceedings of the conference on Design, automation and test in Europe
Penelope: The NBTI-Aware Processor
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
NBTI-Aware Clustered Power Gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Buffering of frequent accesses for reduced cache aging
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Leakage power and circuit aging cooptimization by gate replacement techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TG-based technique for NBTI degradation and leakage optimization
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Static NBTI Reduction Using Internal Node Control
ACM Transactions on Design Automation of Electronic Systems (TODAES)
M-IVC: Applying multiple input vectors to co-optimize aging and leakage
Microelectronics Journal
Application-specific memory partitioning for joint energy and lifetime optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, reducing leakage power remains to be one of the design goals. Because both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input vectors, Input Vector Control (IVC) technique may be adopted to mitigate leakage and NBTI. However, IVC technique is in-effective for larger circuits. Therefore, in this paper, we propose two fast gate replacement algorithms together with optimal input vector selection to simultaneously mitigate leakage power and NBTI induced circuit degradation: Direct Gate Replacement (DGR) algorithm and Divide and Conquer Based Gate Replacement (DCBGR) algorithm. Our experimental results on 20 benchmark circuits at 65nm technology node reveal that: 1) Both DGR and DCBGR algorithms outperform pure IVC about on average 20% for three different object functions: leakage power reduction only, NBTI mitigation only, and leakage/NBTI co-optimization. 2) The DCBGR algorithm leads to better optimization results and save on average 100X runtime compared with the DGR algorithm.