Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Exact and heuristic approaches to input vector control for leakage power reduction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Guest Editorial: Current Trends in Low-Power Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
NBTI-Aware Clustered Power Gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Proceedings of the Conference on Design, Automation and Test in Europe
Minimization of NBTI performance degradation using internal node control
Proceedings of the Conference on Design, Automation and Test in Europe
Gate replacement techniques for simultaneous leakage and aging optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Controlling NBTI degradation during static burn-in testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Leakage power and circuit aging cooptimization by gate replacement techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TG-based technique for NBTI degradation and leakage optimization
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
NBTI mitigation by giving random scan-in vectors during standby mode
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Impact of NBTI on performance of domino logic circuits in nano-scale CMOS
Microelectronics Journal
Aging analysis at gate and macro cell level
Proceedings of the International Conference on Computer-Aided Design
Static NBTI Reduction Using Internal Node Control
ACM Transactions on Design Automation of Electronic Systems (TODAES)
M-IVC: Applying multiple input vectors to co-optimize aging and leakage
Microelectronics Journal
Variation-aware supply voltage assignment for simultaneous power and aging optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Workload assignment considering NBTI degradation in multicore systems
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
Proceedings of the International Conference on Computer-Aided Design
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As technology scales, Negative Bias Temperature Instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, we first investigate the impact of NBTI on PMOS devices and propose a novel temporal performance degradation model for digital circuits considering the temperature difference between active and standby mode. For the first time, the impact of input vector control (to minimize standby leakage) on the NBTI is investigated. Minimum leakage vectors, which lead to minimum circuit performance degradation and remains maximum leakage reduction rate, are selected and used during the standby mode. Furthermore, the potential to save the circuit performance degradation by internal node control techniques during circuit standby mode is discussed. Our simulation results show that: 1) the active and standby time ratio and the standby mode temperature have considerable impact on the circuit performance degradation; 2) the NBTI-aware IVC technique leads to an average 3% savings of the total circuit degradation; while the potential of internal node control may lead to 10% savings of the total circuit degradation.