A physical alpha-power law MOSFET model
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Combating NBTI Degradation via Gate Sizing
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
Proceedings of the conference on Design, automation and test in Europe
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Penelope: The NBTI-Aware Processor
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
NBTI resilient circuits using adaptive body biasing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Aging-resilient design of pipelined architectures using novel detection and correction circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Combating Aging with the Colt Duty Cycle Equalizer
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient selection and analysis of critical-reliability paths and gates
Proceedings of the great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High- Metal-Gate Devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Static NBTI Reduction Using Internal Node Control
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level
DSN '12 Proceedings of the 2012 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
Representative critical reliability paths for low-cost and accurate on-chip aging evaluation
Proceedings of the International Conference on Computer-Aided Design
Timing Analysis and Optimization of Sequential Circuits
Timing Analysis and Optimization of Sequential Circuits
Proceedings of the Conference on Design, Automation and Test in Europe
SlackProbe: a low overhead in situ on-line timing slack monitoring methodology
Proceedings of the Conference on Design, Automation and Test in Europe
Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging
Proceedings of the Conference on Design, Automation and Test in Europe
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
NBTI mitigation by optimized NOP assignment and insertion
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Low power aging-aware register file design by duty cycle balancing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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As CMOS technology scales down into the nanometer regime, designers have to add pessimistic timing margins to the circuit as guardbands to avoid timing violations due to various reliability effects, in particular accelerated transistor aging. Since aging is workload-dependent, the aging rates of different paths are non-uniform, and hence, design time delay-balanced circuits become significantly unbalanced after some operational time. In this paper, an aging-aware logic synthesis approach is proposed to increase circuit lifetime with respect to a specific guardband. Our main objective is to optimize the design timing with respect to post-aging delay in a way that all paths reach the assigned guardband at the same time. In this regard, in an iterative process, after computing the post-aging delays, the lifetime is improved by putting tighter timing constraints on paths with higher aging rate and looser constraints on paths which have less post-aging delay than the desired guarband. The experimental results shows that the proposed approach improves circuit lifetime in average by more than 3X with negligible impact on area. Our approach is implemented on top of a commercial synthesis toolchain, and hence scales very well.