Reliability challenges for 45nm and beyond
Proceedings of the 43rd annual Design Automation Conference
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
Representative path selection for post-silicon timing prediction under variability
Proceedings of the 47th Design Automation Conference
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
In-field aging measurement and calibration for power-performance optimization
Proceedings of the 48th Design Automation Conference
Efficient selection and analysis of critical-reliability paths and gates
Proceedings of the great lakes symposium on VLSI
IEEE Journal on Selected Areas in Communications
Proceedings of the International Conference on Computer-Aided Design
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Aging of transistors degrades circuit performance and can potentially lead to functional failure in the field. This has become a major reliability concern especially when technology further scales to 45 nm and below. It is thus necessary to design on-chip structures that can provide accurate aging evaluation with no performance penalty. In this paper, we propose a novel methodology to accurately evaluate aging in the field. Representative Critical Reliability Paths (RCRP-s) are synthesized as a stand-alone circuit to represent the aging of critical reliability paths, which are defined as paths that can potentially become critical at some point in time due to aging. By monitoring the RCRPs, aging of the critical reliability paths can be efficiently and accurately evaluated with no impact on the normal operation of the chip. The aging evaluation results can then be exploited to guide on-chip performance calibration to ensure lifetime reliability. Simulation results demonstrate the efficiency of the proposed structure.